? semiconductor components industries, llc, 2011 august, 2011 ? rev. 2 1 publication order number: nup3115upmu/d nup3115upmu transient voltage suppressors low capacitance esd protection for high speed data the three ? line voltage transient suppressor array is designed to protect voltage ? sensitive components that require ultra ? low capacitance from esd and transient voltage events. this device features a common anode design which protects three independent high speed data lines and a v cc power line in a single six ? lead udfn low profile package. excellent clamping capability, low capacitance, low leakage, and fast response time make these parts ideal for esd protection on designs where board space is at a premium. because of its low capacitance, it is suited for use in high frequency desi gns such as a usb 2.0 high speed. features ? low capacitance 0.8 pf ? udfn package, 1.6 x 1.6 mm ? low profile of 0.50 mm for ultra slim design ? stand off voltage: 5.5 v ? low leakage ? protects up to three data lines plus a v cc pin ? v cc pin = 15 v protection ? d 1 , d 2 , and d 3 pins = 6.4 v minimum protection ? iec61000 ? 4 ? 2: level 4 esd protection ? this is a pb ? free device typical applications ? usb 2.0 high ? speed interface ? cell phones ? mp3 players ? sim card protection maximum ratings (t j = 25 c, unless otherwise specified) symbol rating value unit i pk peak pulse current v cc diode 8x20 sec double exponential waveform 5.0 a t j operating junction temperature range ? 40 to 125 c t stg storage temperature range ? 55 to 150 c t l lead solder temperature ? maximum (10 seconds) 260 c esd iec 61000 ? 4 ? 2 contact 8000 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. see application note and8308/d for further description of survivability specs. udfn6 1.6x1.6 mu suffix case 517ap http://onsemi.com device package shipping ? ordering information NUP3115UPMUTAG udfn6 (pb ? free) 3000/tape & reel 1 3 v cc d 3 2 d 2 d 1 4 nc 5 6 nc pin connections ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. p3 m 1 p3 = specific device code m = date code = pb ? free package (note: microdot may be in either location) gnd marking diagram 1 6 d 1 d 2 d 3 v cc 6.8v 16v 6.8v 6.8v
nup3115upmu http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current i f forward current v f forward voltage @ i f p pk peak power dissipation c max. capacitance @ v r = 0 and f = 1.0 mhz *see application note and8308/d for detailed explanations of datasheet parameters. uni ? directional tvs i pp i f v i i r i t v rwm v c v br v f electrical characteristics (t j = 25 c, unless otherwise specified) parameter conditions symbol min typ max unit reverse working voltage (d 1 , d 2 , and d 3 ) (note 1) v rwm1 ? ? 5.5 v reverse working voltage (v cc ) (note 1) v rwm2 ? ? 12 v breakdown voltage (d 1 , d 2 , and d 3 ) i t = 1 ma, (note 2) v br 6.0 6.8 8.0 v breakdown voltage (v cc ) i t = 1 ma, (note 2) v br2 15 16 16.8 v reverse leakage current (d 1 , d 2 , and d 3 ) @ v rwm1 i r ? ? 1.0 a reverse leakage current (d 1 , d 2 , and d 3 ) @ 3.3 v i r ? ? 85 na reverse leakage current (v cc ) @ v rwm2 i r ? ? 1.0 a clamping voltage (d 1 , d 2 , and d 3 ) i pp = 1 a v c ? 9.4 ? v clamping voltage (v cc ) i pp = 1 a v c ? 18.5 ? v clamping voltage (v cc ) i pp = 3 a v c ? 22 ? v junction capacitance (d 1 , d 2 , and d 3 ) v r = 0 v, f = 1 mhz (line to gnd) c j ? 0.8 1.0 pf clamping voltage per iec 61000 ? 4 ? 2 (note 4) vc figure 1 and 2 v 1. tvs devices are normally selected according to the working peak reverse voltage (v rwm ), which should be equal or greater than the dc or continuous peak operating voltage level. 2. v br is measured at pulse test current i t . 3. surge current waveform per figure 5. 4. typical waveform. for test procedure see figures 3 and 4 and application note and8307/d. figure 1. esd clamping voltage screenshot positive 8 kv contact per iec61000 ? 4 ? 2 figure 2. esd clamping voltage screenshot negative 8 kv contact per iec61000 ? 4 ? 2
nup3115upmu http://onsemi.com 3 iec 61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000 ? 4 ? 2 spec figure 4. diagram of esd test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d. figure 5. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s
nup3115upmu http://onsemi.com 4 package dimensions udfn6, 1.6x1.6, 0.5p case 517ap ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 e2 bottom view b e 6x 0.10 b 0.05 a c c k 6x note 3 2x 0.10 c pin one reference top view 2x 0.10 c 6x a a1 (a3) 0.05 c 0.05 c c seating plane side view l 6x 1 3 5 6 dim min max millimeters a 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.20 0.30 d 1.60 bsc d2 1.10 1.30 e 1.60 bsc e2 0.45 0.65 e 0.50 bsc k 0.20 ??? l 0.20 0.40 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. mounting footprint* l1 detail a 1.26 0.61 0.50 pitch 0.52 6x 1.90 dimensions: millimeters 0.32 1 6x soldermask defined l1 0.00 0.15 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nup3115upmu/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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